EU-funded project develops microchip specification language
An EU-funded project has developed a breakthrough microchip specification language that will enable the replacement of unclear English with a mathematically precise description of processor
functions and design.
The design of a microchip is a tricky task. First of all there is the question of functionality. Engineers describe, in minute detail and in plain English what a particular microchip must do.
This is an essential task detailing the chip specifications for each stage of the microchip creation process: design, fabrication and verification.
At each development stage, engineers are obliged to turn the English specification list into a mathematically precise function set. The problem is that English is not a mathematically precise
language. Therefore, problems of interpretation are very common.
The problem is exacerbated by the fact that each stage uses different languages, with languages varying between microchip companies. This makes the whole process of microprocessor design hugely
inefficient, costly and prone to error.
‘Before property specification language (PSL) there was no industry standard for describing microchip properties,’ explains Cindy Eisner, coordinator of the Property-based system design
(PROSYD) project at the IBM Haifa Research Laboratory, Israel. ‘Now the IEEE [Institute of Electrical and Electronics Engineers, Inc] has adopted PSL as a standard specification language. So,
we now have an industry standard for microprocessor design,’ she added.
EU-funded PROSYD’s mission was first to create tools to deploy PSL for chip design, fabrication and verification. The project then used these tools to demonstrate PSL’s benefits. Finally, it
sought to foster a revolution in chip design by promoting PSL as a new industry standard.
The project succeeded in its mission to reduce design errors by 50% and increase design efficiency. At the end of the two-year ?7 million project, PROSYD demonstrated a staggering reduction in
design errors of up to 100%, while at the same time increasing design efficiency by 16 to 22%.
After designers become more familiar with the new toolset and language, an even more impressive gain in efficiency can be expected, suggested Dr Eisner.
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